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面积优化
R2026a通过应用面积优化减少目标 FPGA 或 SoC 器件上设计的资源使用。您可以通过使用 RAM 映射、资源复用、流式传输和其他面积优化来减少设计所需的面积。有关面积优化的概述，请参阅Introduction to Optimizations in HDL Coder。
主题
RAM 映射
- Apply RAM Mapping to Optimize Area
Map elements to RAM to optimize area on your target hardware. - Manage How HDL Coder Maps RAM
Learn how HDL Coder™ settings affect RAM mapping. - RAM Mapping with the MATLAB Function Block
How to use RAM mapping optimization withMapPersistentVarsToRAMparameter for MATLAB Function blocks in your model. - Map Matrices to ROM
Map matrices to implement ROM in MATLAB and Simulink.
资源复用、流式传输和其他面积优化
- Resource Sharing
How to use resource sharing to save chip area. - Streaming
What is streaming and how to use the optimization to save resources. - Find Feedback Loops
Highlight feedback loops that are inhibiting optimizations. - Subsystem Optimizations for Filters
Select resource sharing and pipeline optimization options. - HDL Optimizations Across MATLAB Function Block Boundary Using MATLAB Datapath Architecture
Apply optimizations inside and across MATLAB Function blocks with other Simulink® blocks. - Configure Custom Synthesis Attributes for Simulink Blocks
This example shows how to configure custom synthesis attributes for a Simulink model using the command-line interface and propagate them to the generated HDL code. - Use Synthesis Attributes to Map Adders to DSPs on FPGAs
Apply synthesis attributes to map adders to dedicated DSP slices for optimized FPGA implementation. (自 R2026a 起)
精选示例
Get Started with RAM and ROM in Simulink
Configure RAM blocks in Simulink® to generate synthesizable HDL code by using HDL Coder™. The generated code can be mapped by synthesis tools to dedicated RAM resources available in FPGA devices. This example also shows how to model ROM behavior in Simulink.
Streaming: Area Optimization
Use the subsystem level streaming optimization in HDL Coder™.
Resource Sharing for Area Optimization
Use the subsystem level sharing optimization in HDL Coder™.
Single-Rate Resource Sharing Architecture
How HDL Coder™ generates a single-rate architecture from a model to manage the execution of operations in the context of clock-rate pipelining and resource sharing. When you apply resource sharing to blocks in your design, HDL Coder decides the architecture to use based on the sample rate of the regions where sharing occurs. If resource sharing occurs in a region of the design that operates at the fastest base sample rate, then HDL Coder synthesizes a local multi-rate architecture, as described in Resource Sharing for Area Optimization. In this example, the shared resources are in a region that operates at a slower sample rate, so HDL Coder applies clock-rate pipelining and synthesizes a single-rate architecture.
Improve Resource Sharing with Design Modifications
Improve opportunities for resource sharing to optimize your model design by making certain modifications to your design. Resource sharing is an HDL Coder optimization that improves area utilization in the design on the target FPGA device. The optimization identifies multiple functionally equivalent resources and replaces them with a single resource. For more information, see Resource Sharing.
Improve Resource Sharing with Clone Detection and Replacement
Automatically identify and replace recurring patterns by using the 克隆件检测器 (Simulink Check) app. Consequently, it also improves opportunities for optimizing the model by using resource sharing. The Clone Detector app refactors models by identifying clones in a design and replacing clones with links to subsystem blocks in a library. This example uses a model that has already been modified for optimal resource sharing by using the Clone Detector app. To learn more about these modifications, see Improve Resource Sharing with Design Modifications.
