支持的模块和数据类型
R2026b支持的模块库和数据类型
HDL Coder 模块库包含许多基本模块，您可将其添加到 Simulink® 建模环境并开发 HDL 算法。这些模块包括输入源、输出信宿及执行基础到复杂数学和三角运算的模块。
HDL Coder 模块库包含许多基本模块，您可将其添加到 Simulink 建模环境并开发 HDL 算法。这些模块包括输入源、输出信宿及执行基础到复杂数学和三角运算的模块。
要过滤 Simulink 库浏览器以仅显示 HDL 支持的模块，请输入 hdllib。本节列出的模块包括仅在 HDL Coder 库中可用的模块。Add 和 Product 等模块在库浏览器的 Simulink 库中提供。
有关过滤后的支持 HDL 代码生成的 Simulink 模块的列表，请参阅 Simulink 模块列表（HDL 代码生成）。
函数
hdllib | 显示与 HDL 代码生成兼容的模块 |
模块
 | Bit Concat | 将最多 128 个输入字串联成单个输出 |
 | Bit Reduce | 对所有输入信号位进行 AND、OR 或 XOR 位归约，结果为单个位 |
 | Bit Rotate | 按位的位置旋转输入信号 |
 | Bit Shift | 输入信号的逻辑或算术移位 |
 | Bit Slice | 从输入信号返回连续位字段 |
 | Bits to Word | Convert vector of bits to integer (自 R2023a 起) |
 | Word to Bits | Converts real numbers to vector of bits (自 R2023a 起) |
 | Deserializer1D | Convert scalar stream or smaller vectors to vector signal |
 | Multiply-Accumulate | Perform a multiply-accumulate operation on the inputs |
 | Multiply-Add | Multiply-add combined operation |
 | Serializer1D | Convert vector signal to scalar or smaller vectors |
 | Dual Port RAM System | Dual-port RAM that supports simultaneous read and write operations |
 | Dual Rate Dual Port RAM | Dual-port RAM that supports two rates |
 | HDL FIFO | Store sequence of input samples in first in, first out register |
 | Simple Dual Port RAM System | Simple dual-port RAM that supports simultaneous read and write operations |
 | Single Port RAM System | Single-port RAM that supports sequential read and write operations |
 | True Dual Port RAM System | True dual-port RAM that supports simultaneous read and write operations (自 R2023b 起) |
 | Simple Tri Port RAM System | Simple tri-port RAM that supports simultaneous read and write operations (自 R2023b 起) |
 | Unit Delay Enabled Synchronous | Delay input signal by one sample period when external Enable signal is true |
 | Unit Delay Resettable Synchronous | Delay input signal by one sample period when external Reset signal is false |
 | Unit Delay Enabled Resettable Synchronous | Delay input signal by one sample period when external Enable signal is true and external Reset signal is false |
 | Tapped Delay Enabled Synchronous | Delay scalar signal multiple sample periods and output all delayed versions when external Enable signal is true (自 R2023a 起) |
 | Tapped Delay Resettable Synchronous | Delay scalar signal multiple sample periods and output all delayed versions when external Reset signal is false (自 R2023a 起) |
 | Tapped Delay Enabled Resettable Synchronous | Delay scalar signal multiple sample periods and output all delayed versions when external Enable signal is true and external Reset signal is false (自 R2023a 起) |
 | Enabled Delay | Delay input signal by fixed or variable sample periods when external enable signal is true (自 R2024b 起) |
 | Enabled Resettable Delay | Delay input signal by fixed or variable sample periods when external Enable signal is true and external Reset signal is false (自 R2024b 起) |
 | State Control | Specify synchronous reset and enable behavior for blocks with state |
 | Synchronous Subsystem | Represent subsystem that has synchronous reset and enable behavior |
 | Enabled Synchronous Subsystem | Represent enabled subsystem that has synchronous reset and enable behavior |
 | Resettable Synchronous Subsystem | Represent resettable subsystem that has synchronous reset and enable behavior |
 | Sine HDL Optimized and Cosine HDL Optimized | Implement fixed-point sine and cosine wave by using lookup table approach optimized for HDL code generation |
 | HDL Counter | Free-running, count-limited, or modulo hardware counter |
 | Atan2 | 使用 CORDIC 逼近方法计算 Atan2 运算，并进行带延迟的仿真 |
 | Sin | 使用 CORDIC 逼近方法计算正弦运算并带延迟进行仿真 |
 | Cos | 使用 CORDIC 逼近方法计算余弦运算并带延迟进行仿真 |
 | Cos+jSin | 使用 CORDIC 逼近方法计算 Cos+jSin 运算并带延迟进行仿真 |
 | SinCos | 使用 CORDIC 逼近方法计算 SinCos 运算并带延迟进行仿真 |
 | rSqrt | Compute reciprocal square-root operation and simulate with latency |
 | Sqrt | Compute Sqrt operation and simulate with latency |
 | Divide | Compute division operation and simulate with latency |
 | Reciprocal | Compute reciprocal operation and simulate with latency |
主题
模块支持
- Display Blocks for HDL Code Generation in Library Browser
Find blocks that support HDL code generation. - View HDL-Supported Blocks and HDL-Specific Block Documentation
HDL architecture descriptions for supported blocks and list of supported blocks.
数据类型支持
- Supported Data Types and Scope
MATLAB® data type and scope support for HDL code generation. - Signal and Data Type Support
HDL code generation support for signal types and data types.
基础建模
- 创建 HDL 兼容的 Simulink 模型
创建一个模型并检查 HDL 代码生成的兼容性。 - 使用 Simulink 模板进行 HDL 代码生成
使用 Simulink 模型模板进行 HDL 代码生成以创建高效的硬件设计。 - 使用 HDL Coder 实现基于控制信号的数学函数
HDL Coder™ 提供具有基于控制信号的定点数学函数的HDLMathLib模块。这些模块具有指示输入和输出数据是否有效的控制信号。您还可以对这些模块进行带延迟的仿真。
