Supported Blocks and Data Types

R2026b
Supported block library and data types

The HDL Coder block library contains many basic blocks that you can add to your Simulink® modeling environment and develop your HDL algorithm. These blocks include input sources, output sinks, and blocks that perform basic to complex math and trigonometric operations.

The HDL Coder block library contains many basic blocks that you can add to your Simulink modeling environment and develop your HDL algorithm. These blocks include input sources, output sinks, and blocks that perform basic to complex math and trigonometric operations.

To filter the Simulink Library Browser to show only HDL-supported blocks, enter hdllib. The blocks listed in this section include those blocks that are only available in the HDL Coder library. Blocks such as Add and Product are available in the Simulink library in the Library Browser.

For a filtered list of Simulink blocks supported for HDL code generation, see Simulink Block List (HDL Code Generation).

Functions

hdllibDisplay blocks that are compatible with HDL code generation

Blocks

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Bit Concat blockBit ConcatConcatenates up to 128 input words into single output
Bit Reduce blockBit ReduceAND, OR, or XOR bit reduction on all input signal bits to single bit
Bit Rotate blockBit RotateRotate input signal by bit positions
Bit Shift blockBit ShiftLogical or arithmetic shift of input signal
Bit Slice blockBit SliceReturn field of consecutive bits from input signal
Bits to Word BlockBits to WordConvert vector of bits to integer (Since R2023a)
Word to Bits BlockWord to BitsConverts real numbers to vector of bits (Since R2023a)
Deserializer1D blockDeserializer1DConvert scalar stream or smaller vectors to vector signal
Multiply-Accumulate blockMultiply-AccumulatePerform a multiply-accumulate operation on the inputs
Multiply-Add blockMultiply-AddMultiply-add combined operation
Serializer1D blockSerializer1DConvert vector signal to scalar or smaller vectors
Dual Port RAM System blockDual Port RAM SystemDual-port RAM that supports simultaneous read and write operations
Dual Rate Dual Port RAM blockDual Rate Dual Port RAMDual-port RAM that supports two rates
HDL FIFO blockHDL FIFOStore sequence of input samples in first in, first out register
Simple Dual Port RAM System blockSimple Dual Port RAM SystemSimple dual-port RAM that supports simultaneous read and write operations
Single Port RAM System blockSingle Port RAM SystemSingle-port RAM that supports sequential read and write operations
True Dual Port RAM System blockTrue Dual Port RAM SystemTrue dual-port RAM that supports simultaneous read and write operations (Since R2023b)
Simple Tri Port RAM System blockSimple Tri Port RAM SystemSimple tri-port RAM that supports simultaneous read and write operations (Since R2023b)
Unit Delay Enabled Synchronous blockUnit Delay Enabled SynchronousDelay input signal by one sample period when external Enable signal is true
Unit Delay Resettable Synchronous blockUnit Delay Resettable SynchronousDelay input signal by one sample period when external Reset signal is false
Unit Delay Enabled Resettable Synchronous blockUnit Delay Enabled Resettable SynchronousDelay input signal by one sample period when external Enable signal is true and external Reset signal is false
Tapped Delay Enabled Synchronous BlockTapped Delay Enabled SynchronousDelay scalar signal multiple sample periods and output all delayed versions when external Enable signal is true (Since R2023a)
Tapped Delay Resettable Synchronous BlockTapped Delay Resettable SynchronousDelay scalar signal multiple sample periods and output all delayed versions when external Reset signal is false (Since R2023a)
Tapped Delay Enabled Resettable Synchronous BlockTapped Delay Enabled Resettable SynchronousDelay scalar signal multiple sample periods and output all delayed versions when external Enable signal is true and external Reset signal is false (Since R2023a)
Enabled Delay blockEnabled DelayDelay input signal by fixed or variable sample periods when external enable signal is true (Since R2024b)
Enabled Resettable Delay blockEnabled Resettable DelayDelay input signal by fixed or variable sample periods when external Enable signal is true and external Reset signal is false (Since R2024b)
State Control blockState ControlSpecify synchronous reset and enable behavior for blocks with state
Synchronous Subsystem blockSynchronous SubsystemRepresent subsystem that has synchronous reset and enable behavior
Enabled Synchronous Subsystem blockEnabled Synchronous SubsystemRepresent enabled subsystem that has synchronous reset and enable behavior
Resettable Synchronous Subsystem blockResettable Synchronous SubsystemRepresent resettable subsystem that has synchronous reset and enable behavior
Sine HDL Optimized blockSine HDL Optimized and Cosine HDL OptimizedImplement fixed-point sine and cosine wave by using lookup table approach optimized for HDL code generation
HDL Counter blockHDL CounterFree-running, count-limited, or modulo hardware counter
HDL Math Atan2 BlockAtan2Compute Atan2 operation using CORDIC approximation method and simulate with latency
HDL Math Sine BlockSinCompute sine operation using CORDIC approximation method and simulate with latency
HDL Math Cosine BlockCosCompute cosine operation using CORDIC approximation method and simulate with latency
HDL Math Cos+jSin BlockCos+jSinCompute Cos+jSin operation using CORDIC approximation method and simulate with latency
HDL Math SinCos BlockSinCosCompute SinCos operation using CORDIC approximation method and simulate with latency
HDL Math rSqrt BlockrSqrtCompute reciprocal square-root operation and simulate with latency
HDL Math Sqrt BlockSqrtCompute Sqrt operation and simulate with latency
HDL Math Divide BlockDivideCompute division operation and simulate with latency
HDL Math Reciprocal BlockReciprocalCompute reciprocal operation and simulate with latency

Topics

Block Support

Data Type Support

Basic Modeling