生成测试

生成测试集以满足模型和代码覆盖率以及自定义测试准则

测试生成会为模型生成输入值序列以满足测试准则，例如模型覆盖率。Simulink^® Design Verifier™ 可根据基于需求的测试扩展现有模型覆盖率信息。它会生成附加测试输入序列，以满足在基于需求的测试期间未满足的覆盖率目标。使用这些测试输入可以更好地了解缺失需求以及创建更完整的测试工具。

模块

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测试用例生成中使用的模块

Test Condition	Constrain signal values in test cases
Test Objective	Define custom objectives that signals must satisfy in test cases
Detector	Detect true duration on input and construct output true duration based on output type
Extender	Extend true duration of input
Implies	Specify condition that produces a certain response
Within Implies	Verify response occurs within desired duration
Verification Subsystem	Specify proof or test objectives without impacting simulation results or generated code

函数

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测试用例生成中使用的函数

`sldvoptions`	Create design verification options object
`sldv.condition`	Test condition function for Stateflow charts and MATLAB Function blocks
`sldv.test`	Test objective function for Stateflow charts and MATLAB Function blocks
`sldvextract`	Extract subsystem or subchart contents into new model for analysis
`sldvtimer`	Identify, change, and display timer optimizations
`sldvoptions`	Create design verification options object
`sldvrun`	Analyze model
`sldvlogsignals`	Log simulation input port values
`sldvgencov`	Analyze models to obtain missing model coverage
`sldvgenspreadsheet`	Generate spreadsheet containing test cases (自 R2022b 起)
`sldvruntest`	Simulate model by using input data
`sldvruntestopts`	Generate simulation or execution options for `sldvruntest` or `sldvruncgvtest`
`sldvharnessopts`	Default options for `sldvmakeharness`
`sldvmakefilter`	Generate filter file containing justification rules for objectives with `Unsatisfiable`, `Dead Logic`, `Falsified`, `Falsified - No Counterexample`, or `Error - Needs Simulation` status in `sldvData` file (自 R2022a 起)
`sldvmakeharness`	Generate harness model
`sldvmergeharness`	Merge test cases and initializations into one harness model
`sldvreport`	Generate Simulink Design Verifier report
`sldvchecksum`	Returns checksum of model (自 R2021a 起)

主题

入门知识

What Is Test Case Generation?
Brief overview of test case generation with Simulink Design Verifier.
Workflow for Test Case Generation
Outlines a process for generating test cases for your model.
When to Extend Existing Test Cases
Explains when to extend existing test cases to create a complete test suite.
Creating and Executing Test Cases
This example shows how to use Simulink® Design Verifier™ functions to log input signals, create a harness model, generate test cases for missing coverage, merge harness models, and execute test cases.
Export Test Cases to Simulink Test
Describes how to generate test cases in Simulink Test™ using Simulink Design Verifier analysis results, which can be generated by property proving, design error detection, and test case generation.
Export Tests from Models That Contain Requirements Table Blocks with Simulink Design Verifier
Automate test generation and execution by using models that contain Requirements Table blocks.
Defining and Extending Existing Tests Cases
This example shows how Simulink® Design Verifier™ can extend test cases with additional time steps to efficiently generate complete test suites.
Use Test Generation Advisor to Identify Analyzable Components
Use the Test Generation Advisor to guide model and component analysis.
Extend Existing Test Cases by Reusing Model Representation
Reanalyze a model by reusing the model representation.
Basic Workflow for Enhanced MCDC Analysis
Workflow to generate test cases for enhanced Modified Condition Decision Coverage (MCDC) coverage objectives.

为模型决策覆盖率生成测试

Model Coverage Objectives for Test Generation
Test cases are generated to drive your model to satisfy condition, decision, modified condition/decision (MCDC), and custom coverage objectives.
Generate Test Cases for Model Decision Coverage
An example that walks you through the process of generating the test cases for a model.
Specify Parameter Configuration for Full Coverage
An example of how to specify parameter constraint values to achieve full model coverage.
Generate Test Cases for a Subsystem
Analyze an individual subsystem.
Generate Test Cases for a Reusable Library Subsystem
Analyze a reusable library subsystem.
Extend Test Cases for Model with Temporal Logic
Extends existing test cases to analyze a model that uses temporal logic.
Extend Test Cases for Closed-Loop System
Extends existing test cases to analyze a closed-loop system in a model.
Extend Test Cases for Modified Model
Extends existing test cases for a model that you have previously analyzed and then modified.
Extend an Existing Test Suite
This example shows how to use Simulink® Design Verifier™ to extend an existing test suite to obtain missing model coverage.
Extend Existing Test Cases After Applying Parameter Configurations
This example shows how to achieve missing coverage by extending existing test cases after applying parameter configurations.
Enhance Model Coverage of Older Release Models
Explains how to use cross release workflow for model upgrade by using Simulink Design Verifier.

为模型中的自定义代码生成测试

Configuring S-Function for Test Case Generation
This example shows how to compile an S-Function to be compatible with Simulink® Design Verifier™ for test case generation.
Test Generation on Model with C Caller Block
Test generation on a model with a C Caller block and custom C code.
Test Generation for Custom Code in MATLAB Function Block
Simulink Design Verifier analysis supports models that call custom code from MATLAB^® function blocks by using coder.ceval.
Support Limitations and Considerations for S-Functions and C/C++ Code
Describes limitations and considerations of S-functions and Generated Code in Simulink Design Verifier.

为可分析的模型组件生成测试

Generate Test Cases for Model Blocks
Generate Test Cases for Model Reference blocks.
Use Test Generation Advisor to Identify Analyzable Components
Use the Test Generation Advisor to guide model and component analysis.
Generate Tests for Model Block Component by Using Default Simulation
This example shows how to use Simulink® Design Verifier™ to generate test cases for a Model block by using a default top model simulation.
Achieve Missing Coverage in Subsystems and Model Blocks
Explains how to convert subsystems to Model blocks before attempting to achieve missing coverage.
Achieve Missing Coverage in Referenced Model
Achieves missing coverage data in a referenced model and combines it with coverage data for the top-level model.
Achieve Missing Coverage in Closed-Loop Simulation Model
Achieves missing coverage data in a closed-loop simulation model.
Analyze Coverage for Lookup Table Boundary Values
Describes how to generate tests for lookup table boundary value coverage.
Using Existing Coverage Data During Subsystem Analysis
This example shows how Simulink® Design Verifier™ can target its analysis to a single subsystem within a continuous-time closed-loop simulation and generate test cases for missing coverage in that subsystem.
Achieve Coverage in Models with Variable-Size Inputs
This example shows you how to achieve model coverage in models with variable-size input signals by using Simulink Design Verifier™.
Achieve Missing Coverage in Generated Code of RLS
This example shows you how to use Simulink® Design Verifier™ to generate test cases that achieve full coverage.
Achieve Missing Coverage in Custom Code
This example shows you how to test for missing coverage in custom code.
Inspect Test Generation Objectives by Using Model Slicer
Inspect Test Generation Objectives using Model Slicer.

生成测试以完成生成代码的覆盖率分析

Code Coverage Test Generation
This example shows how to use Simulink® Design Verifier™ to generate test cases to obtain complete code coverage.
Generate Test Cases for Embedded Coder Generated Code
Outlines a process for generating test cases for generated code.

精选示例

Model Coverage Test Generation

Generate test cases that achieve complete model coverage for a debouncer. The outcome of each model coverage point in this example model is a test objective. If you configure Simulink Design Verifier to generate the fewest test cases, it will satisfy as many objectives as possible in each test case.

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Fuel Rate Controller Logic

Generate test cases that satisfy Decision, Condition, and MCDC coverage. Simulink® Design Verifier™ automatically generates test data and proves properties of models. It produces sequences of input values that satisfy a testing criteria or demonstrate a counterexample of a proof. The configuration options associated with the model specify the objectives of the analysis. When you analyze the model, Simulink Design Verifier uses exhaustive searching techniques to generate input data. When successful, it generates test data and creates a new harness model containing a Signal Editor block with the data values that satisfy the analysis objectives. NOTE: The complexity of this model might prevent test generation from completing in the allotted time. You can stop test generation and generate partial results, or you can extend the time limit by editing the Simulink Design Verifier options.

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Cruise Control Test Generation

Generate test cases that achieve complete model coverage. By default, Simulink® Design Verifier™ generates test cases that satisfy objectives in the fewest steps. One of the test objectives forces the discrete integrator in the PI controller to exceed its upper limit. When you run Simulink Design Verifier without constraints, the limit is exceeded in a single step by forcing speed to be 500. The constraint on speed limits the values in test cases between 0 and 100. This forces the test cases to take several samples to exceed the integrator limit.

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Flip Flop Test Generation

Generate test cases that achieve complete model coverage for a flip-flop. The outcome of each model coverage point in this example model is a test objective. If you configure Simulink Design Verifier to generate the fewest test cases, it will satisfy as many objectives as possible in each test case.

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