MATLAB for FPGA, ASIC, and SoC Production Design and Verification

Refine algorithms with hardware architecture and generate code and verification models using MATLAB and Simulink

Multiple members of FPGA, ASIC, or SoC projects can collaborate on key early decisions at a high-level of abstraction, then generate code and models to jump-start implementation.

With MATLAB® and Simulink® you can:

  • Model and simulate a variety of architecture choices
  • Refine algorithms top-down toward implementation
  • Converge on fixed-point quantization
  • Generate production-quality RTL and embedded C code
  • Generate verification models for use in digital or analog simulation environments
  • Adhere to functional safety certification workflows

“Simulink helps system architects and hardware designers communicate. It is like a shared language that enables us to exchange knowledge, ideas, and designs. Simulink and HDL Coder enable us to focus on developing our algorithms and refining our design via simulation, not on checking VHDL syntax and coding rules.”

Marcel van Bakel, Philips Healthcare

Using MATLAB for Production Design and Verification

SoC Architecture and Top-Down Design

Algorithm developers can collaborate with system architects and digital, analog/mixed-signal, and verification engineers to explore architecture options at a high-level of abstraction. This lets you and your team experiment with partitioning strategies then incrementally refine the partitions with implementation detail such as hardware micro-architecture and fixed-point quantization. More than 300 blocks support HDL code generation, including production-proven hardware IP blocks and subsystems.

Throughout this top-down process, you can continuously integrate more detailed models for simulation in the system context to eliminate functional and performance issues early. The process lets you create and manage suites of system-level test cases and measure model coverage so you can be confident that your implementation is successful.

Explore implementation tradeoffs at a high-level, verifying each refinement step versus the previously known, good version.


Generate SystemVerilog DPI or UVM components to speed verification environment creation.

Verification Model Generation

You can generate models to speed RTL verification environment creation directly from MATLAB functions or Simulink models that support C code generation. This ensures that you accurately capture the high-level behavior of reference models and stimuli for RTL simulation. If the high-level design changes, you can re-generate the models.

These verification components use the SystemVerilog Direct Programming Interface (DPI), so you can use them in any simulator that supports SystemVerilog. You can optionally generate a Universal Verification Methodology (UVM) component from Simulink if your RTL verification environment uses UVM.


Production Code Generation

Legacy design processes often introduce bugs during the manual processes of writing a specification document and writing code based on that document. Once you have performed system-level verification with MATLAB and Simulink, you can generate HDL and C code directly from these verified implementation models.

The generated HDL is readable, traceable back to its source model, and is target-independent. You can control speed optimizations such as pipeline insertion, area optimizations like resource sharing, and various coding styles and structure options. While synthesis tools from Xilinx® and Intel® can run automatically from the code generation menu, you can generate scripts to run any FPGA or ASIC synthesis tool.

Readable HDL code, including model comments, with line-level traceability between the code and model.


Checking a hardware subsystem for compliance with DO-254 modeling standards.

Functional Safety

If your project requires compliance with a functional safety standard, then workflows for FPGA, ASIC, and SoC development are included in kits for DO-254, ISO 26262, and IEC 61508. These workflows include running Model Advisor with built-in checks to ensure your model complies with the appropriate standard’s requirements.

The generated HDL and C code is readable and traceable back to the model and requirements to ease code review. You can use various techniques such as back-to-back testing with cosimulation or FPGA-in-the-loop to help satisfy verification requirements.